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oki semiconducto r fedl9207-02 issue date: may 17, 2005 ML9207-XX 5 7 dot character 24-digit display controller/driver with character ram 1/35 general description the ML9207-XX is a dot matrix vacuum fluorescent display tube controller driver ic which displays characters, numerics and symbols. dot matrix vacuum fluorescent display tube drive signals are generated by serial data sent from a micro-controller. a display system is easily realized by internal rom and ram for character display. the ML9207-XX has low power consumption since it is made by cmos process technology. -01 is available as a general-purpose code. custom codes are provided on customer's request. features ? logic power supply (v dd ) : 3.3 v 10% or 5.0 v 10% ? fluorescent display tube drive power supply (v disp ) : 3.3 v 10% or 5.0 v 10% ? fluorescent display tube drive power supply (v fl ) : ?20 to ?60 v ? vfd driver output current (vfd driver output can be connected directly to the fluorescent display tube. no pull-down resistor is required.) ? segment driver (seg1 to seg35) : ?5.0 ma (v fl = ?60 v) ? segment driver (ad1 to ad4) : ?10.0 ma (v fl = ?60 v) ? grid driver (com1 to com24) : ?50.0 ma (v fl = ?60 v) ? general output port output current output driver (p1 to p4) : 1.0 ma (v dd = 3.3 v 10%) 2.0 ma (v dd = 5.0 v 10%) ? content of display ? cgrom 5 7 dots : 240 types (character data) ? cgram 5 7 dots : 16 types (character data) ? adram 24 (display digit) 4 bits (symbol data) ? dcram 24 (display digit) 8 bits (register for character data display) ? general output port 4 bits (static operation) ? display control function ? display digit : 9 to 24 digits ? display duty (brightness adjustment) : 0/1024 to 960/1024 ? all lights on/off ? 4 interfaces with microcontroller : da, cs , cp , reset ? 1-byte instruction execution (excluding data write to ram and display duty set) ? built-in oscillation circuit ? crystal oscillation or ceramic oscillation ? package options: 80-pin qfp package (qfp80-p-1414-0.65-k) (product name : ML9207-XXgp) 80-pin qfp package (qfp80-p-1420-0.80-bk) (product name : ML9207-XXga) xx indicates the code number.
fedl9207-02 oki semiconductor ML9207-XX 2/35 block diagram v dd gnd v fl r ese t da c p c s osc0 osc1 seg1 seg35 ad1 ad4 p1 p4 com1 com24 dcram 24w 8b cgrom cgram 16w 35b adram 24w 4b 8-bit shift register command decoder control circuit timing oscillator timing digit control duty control grid driver port driver ad driver segment driver write address counter read address counter address selector v disp 240w 35b generator1 generator2
fedl9207-02 oki semiconductor ML9207-XX 3/35 schematic diagram of driver output circuit v fl v fl v disp output v disp
fedl9207-02 oki semiconductor ML9207-XX 4/35 pin configuration (top view) nc: no connection 80-pin plastic qfp (qfp80-p-1414-0.65-k) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 ad2 ad1 v disp2 n c v fl2 p4 p 3 p2 p1 v dd d a c p c s r ese t osc1 osc0 g nd v fl1 co m2 4 co m2 3 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 s e g 1 9 s e g 2 0 s e g 21 s e g 22 s e g 2 3 s e g 24 s e g 2 5 s e g 2 6 s e g 27 s e g 2 8 s e g 2 9 seg30 seg31 seg32 s e g33 s e g3 4 s e g35 v disp1 co m1 co m2 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 com22 com21 com20 com19 com18 com17 com16 com15 com14 com13 com12 com11 com10 com9 com8 com7 com6 com5 com4 com3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 ad3 ad4 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg17 seg18
fedl9207-02 oki semiconductor ML9207-XX 5/35 nc: no connection 80-pin plastic qfp (qfp80-p-1420-0.80-bk) com1 41 com2 42 com3 43 com4 44 com5 45 com6 46 com7 47 com8 48 com9 49 com10 50 com11 51 com12 52 com13 53 com14 54 com15 55 com16 56 com17 57 com18 58 com19 59 com20 60 com21 61 com22 62 com23 63 com24 64 v disp1 40 s e g35 39 s e g3 4 38 s e g33 37 s e g3 2 36 s e g3 1 35 s e g30 34 s e g 2 9 33 seg28 32 seg27 31 s e g 2 6 30 s e g 2 5 29 s e g 24 28 s e g 2 3 27 s e g 22 26 s e g 21 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 seg20 seg19 seg18 seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 ad4 ad3 ad2 ad1 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 v fl1 g nd osc0 osc 1 r ese t c s c p d a v dd p1 p2 p 3 p4 v fl2 n c v disp2
fedl9207-02 oki semiconductor ML9207-XX 6/35 pin description pin qfp-1 * qfp-2* symbol type connects to description 3 to 37 5 to 39 seg1 to 35 o fluorescent tube anode electrode fluorescent display tube anode electrode drive output. directly connected to fluorescent display tube and a pull-down resistor is not necessary. i oh > ?5.0 ma 39 to 62 41 to 64 com1 to 24 o fluorescent tube grid electrode fluorescent display tube grid electrode drive output. directly connected to fluorescent display tube and a pull-down resistor is not necessary. i oh > ?50.0 ma 1, 2, 79, 80 1 to 4 ad1 to ad4 o fluorescent tube anode electrode fluorescent display tube anode electrode drive output. directly connected to fluorescent display tube and a pull-down resistor is not necessary. i oh > ?10.0 ma 72 to 75 74 to 77 p1 to p4 o led anode electrode general port output. output of these pins in static operation, so these pins can drive the led. i oh > ?2.0 ma 71 73 v dd 38, 78 40, 80 v disp1 to 2 64 66 gnd 63, 76 65, 78 v fl1 to 2 ? power supply v dd -gnd are power supplies for internal logic. v disp -v fl are power supplies for driving fluorescent tubes. use the same power supply for v dd and v disp . 70 72 da i microcontroller serial data input (positive logic). input from lsb. 69 71 cp i microcontroller shift clock input. serial data is shifted on the rising edge of cp . 68 70 cs i microcontroller chip select input. serial data transfer is disabled when cs pin is "h" level. 67 69 reset l microcontroller reset input. "low" initializes all the functions. initial status is as follows. ? address of each ram ... address "00"h ? data of each ram ......... content is undefined ? display digit .................. 24 digits ? brightness adjustment .. 0/1024 ? all lights on or off ..... off mode ? all outputs .................... "low" level 65 67 osc0 i 66 68 osc1 o crystal or ceramic resonator pins for self-oscillation. (do not apply external clocks to these pins.) connect these pins to the crystal and capacitors or to the ceramic resonator and capacitors. the target oscillation frequency is 4.0 mhz. (note that the device includes the feed back resistor of 1 m ? ) see application circuit. * qfp1 : qfp80-p-1414-0.65-k qfp2 : qfp80-p-1420-0.80-bk
fedl9207-02 oki semiconductor ML9207-XX 7/35 absolute maximum ratings parameter symbol condition rating unit v dd * 1 ?0.3 to +6.5 v supply voltage (1) v disp * 1 ?0.3 to +6.5 v supply voltage (2) v fl ? ?80 to v disp +0.3 v input voltage v in ? ?0.3 to v dd +0.3 v qfp80-p-1414-0.65-k 637 power dissipation p d ta 25c qfp80-p-1420-0.80-bk 764 mw storage temperature t stg ? ?55 to +150 c i o1 com1 to com24 ?60 to 0.0 i o2 ad1 to ad4 ?20 to 0.0 i o3 seg1 to seg35 ?10 to 0.0 output current i o4 p1 to p4 ?4.0 to +4.0 ma *1: use the same power supply for v dd and v disp . recommended operating conditions when the power supply voltage is 5v (typ.) parameter symbol condition min. typ. max. unit supply voltage (1) v dd , v disp ? 4.5 5.0 5.5 v supply voltage (2) v fl ? ?60 ? ?20 v high level input voltage v ih all input pins excluding osc0 pin 0.7 v dd ? ? v low level input voltage v il all input pins excluding osc0 pin ? ? 0.3 v dd v cp frequency f c ? ? ? 2.0 mhz oscillation frequency f osc self-oscillation 3.5 4.0 4.5 mhz frame frequency f fr digit = 1 to 24, self-oscillation 142 163 183 hz operating temperature t op ? ?40 ? +85 c when the power supply voltage is 3.3v (typ.) parameter symbol condition min. typ . max. unit supply voltage (1) v dd , v disp ? 3.0 3.3 3.6 v supply voltage (2) v fl ? ?60 ? ?20 v high level input voltage v ih all input pins excluding osc0 pin 0.8 v dd ? ? v low level input voltage v il all input pins excluding osc0 pin ? ? 0.2 v dd v cp frequency f c ? ? ? 2.0 mhz oscillation frequency f osc self-oscillation 3.5 4.0 4.5 mhz frame frequency f fr digit = 1 to 24, self-oscillation 142 163 183 hz operating temperature t op ? ?40 ? +85 c
fedl9207-02 oki semiconductor ML9207-XX 8/35 electrical ch aracteristics dc characteristics-1 (v dd , v disp = 5.0 v 10%, v fl = ?60v, ta = ?40 to +85c, unless otherwise specified) parameter symbol applied pin condition min. max. unit high level input voltage v ih cs , cp , da, reset ? 0.7 v dd ? v low level input voltage v il cs , cp , da, reset ? ? 0.3 v dd v high level input current i ih cs , cp , da, reset v ih = v dd ?1.0 +1.0 a low level input current i il cs , cp , da, reset v il = 0.0 v ?1.0 +1.0 a v oh1 com1 to 24 i oh1 = ?50.0 ma v disp ?2.0 ? v v oh2 ad1 to ad4 i oh2 = ?10.0 ma v disp ?1.5 ? v v oh3 seg1 to 35 l oh3 = ?5.0 ma v disp ?1.5 ? v high level output voltage v oh4 p1 to p4 i oh4 = ?2.0 ma v dd ?1.0 ? v v ol1 com1 to 24 ad1 to ad4 seg1 to 35 ? ? v fl +1.0 v low level output voltage v ol2 p1 to p4 i ol1 = 2 ma ? 1.0 v i dd1 duty = 960/1024 digit = 1 to 24 all output lights on ? 6 ma supply current i dd2 v dd , v disp f osc = 4 mhz, no load duty = 0/1024 digit = 1 to 9 all output lights off ? 5 ma
fedl9207-02 oki semiconductor ML9207-XX 9/35 dc characteristics-2 (v dd , v disp = 3.3 v 10%, v fl = ?60 v, ta = ?40 to +85c, unless otherwise specified) parameter symbol applied pin condition min. max. unit high level input voltage v ih cs , cp , da, reset ? 0.8 v dd ? v low level input voltage v il cs , cp , da, reset ? ? 0.2 v dd v high level input current i ih cs , cp , da, reset v ih = v dd ?1.0 +1.0 a low level input current i il cs , cp , da, reset v il = 0.0 v ?1.0 +1.0 a v oh1 com1 to 24 i oh1 = ?50.0 ma v disp ?2.0 ? v v oh2 ad1 to ad4 i oh2 = ?10.0 ma v disp ?1.5 ? v v oh3 seg1 to 35 i oh3 = ?5.0 ma v disp ?1.5 ? v high level output voltage v oh4 p1 to p4 i oh4 = ?1.0 ma v dd ?1.0 ? v v ol1 com1 to 24 ad1 to ad4 seg1 to 35 ? ? v fl +1.0 v low level output voltage v ol2 p1 to p4 i ol1 = 1 ma ? 1.0 v i dd1 duty = 960/1024 digit = 1 to 24 all output lights on ? 5 ma supply current i dd2 v dd , v disp f osc = 4 mhz, no load duty = 0/1024 digit = 1 to 9 all output lights off ? 4 ma
fedl9207-02 oki semiconductor ML9207-XX 10/35 ac characteristics-1 (v dd , v disp = 5.0 v 10%, v fl = ?60 v, ta = ?40 to +85c, unless otherwise specified) parameter symbol condition min. max. unit cp frequency f c ? ? 2.0 mhz cp pulse width t cw ? 250 ? ns da setup time t ds ? 250 ? ns da hold time t dh ? 250 ? ns cs setup time t css ? 250 ? ns cs hold time t csh self-oscillation 16 ? s cs wait time t csw ? 250 ? ns data processing time t doff self-oscillation 8 ? s reset pulse width t wres when reset signal is input from microcontroller, etc. externally 250 ? ns reset time t rson ? t oscon ? ns da wait time t rsoff ? 250 ? ns t r t r = 20% to 80% ? 2.0 s all output slew rate t f c i = 100 pf t f = 80% to 20% ? 2.0 s osc duty ratio du osc ? 40 60 % oscillation start-up time t oscon ? * 1 *1 t oscon depends on the type of crystal or resonator. refer to characteristic data of crystal or resonator used. ac characteristics-2 (v dd , v disp = 3.3 v 10%, v fl = ?60 v, ta = ?40 to +85c, unless otherwise specified) parameter symbol condition min. max. unit cp frequency f c ? ? 2.0 mhz cp pulse width t cw ? 250 ? ns da setup time t ds ? 250 ? ns da hold time t dh ? 250 ? ns cs setup time t css ? 250 ? ns cs hold time t csh self-oscillation 16 ? s cs wait time t csw ? 250 ? ns data processing time t doff self-oscillation 8 ? s reset pulse width t wres when reset signal is input from microcontroller, etc. externally 250 ? ns reset time t rson ? t oscon ? ns da wait time t rsoff ? 250 ? ns t r t r = 20% to 80% ? 2.0 s all output slew rate t f c i = 100 pf t f = 80% to 20% ? 2.0 s osc duty ratio du osc ? 40 60 % oscillation start-up time t oscon ? * 1 *1 t oscon depends on the type of crystal or resonator. refer to characteristic data of crystal or resonator used.
fedl9207-02 oki semiconductor ML9207-XX 11/35 timing diagram symbol v dd = 3.3 v 10% v dd = 5.0 v 10% v ih 0.8 v dd 0.7 v dd v il 0.2 v dd 0.3 v dd ? data timing ? reset timing ? output timing all outputs t f t 0.8 v disp 0.2 v fl c s c p da t css t ds t dh t doff t cw valid valid valid valid v ih v il 1/f c t cw t csh t csw v il v ih v il v ih 0.8 v dd v ih 0.0 v v il v ih v il v dd r ese t da t wres t rsoff t rson
fedl9207-02 oki semiconductor ML9207-XX 12/35 ? digit output timing (for 24-dig it display, at a duty of 960/1024) ? osc timing com1 com2 com3 com4 com5 com6 v fl frame cycle t 1 = 24576t display timing t 2 = 960t blank timing t 3 = 64t v disp t=1/ f osc (t 1 = 6.144 ms when f osc = 4.0 mh ) (t 2 = 240 100 0.5 v dd
fedl9207-02 oki semiconductor ML9207-XX 13/35 functional description command list lsb 1st byte msb lsb 2nd byte msb command b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 1 dcram data write x0 x1 x2 x3 x4 1 0 0 c0 c1 c2 c3 c4 c5 c6 c7 c0 c5 c10 c15 c20 c25 c30 * c1 c6 c11 c16 c21 c26 c31 * c2 c7 c12 c17 c22 c27 c32 * c3 c8 c13 c18 c23 c28 c33 * 2 cgram data write x0 x1 x2 x3 * 0 1 0 c4 c9 c14 c19 c24 c29 c34 * 3 adram data write x0 x1 x2 x3 x4 1 1 0 c0 c1 c2 c3 * * * * 4 general output port set p1 p2 p3 p4 * 0 0 1 5 display duty set d0 d1 * * * 1 0 1 d2 d3 d4 d5 d6 d7 d8 d9 6 number of digits set k0 k1 k2 k3 * 0 1 1 7 all lights on/off l h * * * 1 1 1 test mode when data is written to ram (dcram, cgram, adram) continuously, addresses are internally incremented automatically. therefore it is not necessary to specify the 1st byte to write ram data for the 2nd and later bytes. note : the test mode is used for inspection before shipment. this is not a user function. * : don't care xn : address specification for each ram cn : character code specification for each ram pn : general output port status specification dn : display duty specification kn : number of digits specification h : all lights on instruction l : all lights off instruction 2nd byte 3rd byte 4th byte 5th byte 6th byte
fedl9207-02 oki semiconductor ML9207-XX 14/35 positional relationship between segn and adn (one digit) adram written data. corresponds to 2nd byte cgram written data. corresponds to 2nd byte cgram written data. corresponds to 3rd byte cgram written data. corresponds to 4th byte cgram written data. corresponds to 6th byte cgram written data. corresponds to 5th byte c0 ad1 c0 seg1 c5 seg6 c10 seg11 c15 seg16 c20 seg21 c25 seg26 c30 seg31 c1 seg2 c6 seg7 c11 seg12 c16 seg17 c21 seg22 c26 seg27 c31 seg32 c2 seg3 c7 seg8 c12 seg13 c17 seg18 c22 seg23 c27 seg28 c32 seg33 c3 seg4 c8 seg9 c13 seg14 c18 seg19 c23 seg24 c28 seg29 c33 seg34 c4 seg5 c9 seg10 c14 seg15 c19 seg20 c24 seg25 c29 seg30 c34 seg35 c1 ad2 c2 ad3 c3 ad4
fedl9207-02 oki semiconductor ML9207-XX 15/35 data transfer method and command write method display control command and data are written by an 8-bit serial transfer. write timing is shown in the figure below. setting the cs pin to "low" level enables a data transfer. data is 8 bits and is sequentially input into the da pin from lsb (lsb first). as shown in the figure below, data is read by the shift register at the rising edge of the shift clock, which is input into the cp pin. if 8-bit data is input, internal load signals are automatically generated and data is written to each register and ram. therefore it is not necessary to input load signals from the outside. setting the cs pin to "high" disables data transfer. data input from the point when the cs pin changes from "high" to "low" is recognized in 8-bit units. * when data is written to ram (dcram, adram, cgram) continuously, addresses are internally incremented automatically. therefore it is not necessary to specify the 1st byte to write ram data for the 2nd and later bytes. reset function reset is executed when the reset pin is set to "l", (when turning power on, for example) and initializes all functions. initial status is as follows: ? address of each ram ......................................address "00"h ? data of each ram............................................all contents are undefined ? general output port ..........................................a ll general output ports (p1 to p4) go "low" ? display digit.....................................................24 digits ? brightness ad justment ......................................0/ 1024 ? all display lights on or off ...........................off mode ? segment output ................................................all se gment outputs (seg1 to seg35) go "low" ? common output................................................a ll common outputs (com1 to com24) go "low" ? ad output ........................................................all ad outputs (ad1 to ad4) go "low" please set the functions again according to "setting flowchart" after reset. t doff b0 lsb c s c p b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 msb 1st byte lsb msb 2nd byte command and address data t csh b0 b1 b2 b3 b4 b5 b6 b7 lsb msb 2nd byte character code data of the next address character code data when data is written to dcram* da
fedl9207-02 oki semiconductor ML9207-XX 16/35 description of commands and functions 1. dcram data write (specifies the addresses 00h to 1fh of dcram and writes the character codes of cgrom and cgram.) dcram (data control ram) has a 5-bit address to store the character codes of cgrom and cgram. the character code specified by dcram is converted to a 5 7 dot matrix character pattern via cgrom or cgram. (the dcram can store 24 characters.) [command format] to specify the character code of cgrom and cgram continuously to the next address, specify only character codes as follows. the addresses of dcram are automatically incremented. specification of an address is unnecessary. x0 x1 x2 x3 x4 1 0 0 b0 b1 b2 b3 b4 b5 b6 b7 1st byte (1st) lsb msb c0 c1 c2 c3 c4 c5 c6 c7 b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (2nd) lsb msb : selects dcram data write mode and specifies dcram address (ex: specifies dcram address 00h.) : specifies the character codes of cgrom and cgram (written into dcram address 00h) c0 c1 c2 c3 c4 c5 c6 c7 b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (3rd) lsb msb c0 c1 c2 c3 c4 c5 c6 c7 b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (4th) lsb msb : specifies the character codes of cgrom and cgram (written into dcram address 01h) : specifies the character codes of cgrom and cgram (written into dcram address 02h) b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (25th) lsb msb : specifies the character codes of cgrom and cgram (written into dcram address 17h) c0 c1 c2 c3 c4 c5 c6 c7
fedl9207-02 oki semiconductor ML9207-XX 17/35 the character code setting of cgrom and cgram up to 24 digits is completed. to set a character code from dcram address 00h continuously. specify a dummy character code between dcram addresses 18h and 1fh. (to increment the dcram address automatically and set it to 00h) x0 (lsb) to x4 (msb): dcram addresses (5 bits: 24 characters) c0 (lsb) to c7 (msb): character codes of cgrom and cgram (8 bits: 256 characters) [com positions and set dcram addresses] hex x0 x1 x2 x3 x4 com position hex x0 x1 x2 x3 x4 com position 00 0 0 0 0 0 com1 10 0 0 0 0 1 com17 01 1 0 0 0 0 com2 11 1 0 0 0 1 com18 02 0 1 0 0 0 com3 12 0 1 0 0 1 com19 03 1 1 0 0 0 com4 13 1 1 0 0 1 com20 04 0 0 1 0 0 com5 14 0 0 1 0 1 com21 05 1 0 1 0 0 com6 15 1 0 1 0 1 com22 06 0 1 1 0 0 com7 16 0 1 1 0 1 com23 07 1 1 1 0 0 com8 17 1 1 1 0 1 com24 08 0 0 0 1 0 com9 18 0 0 0 1 1 not fixed 09 1 0 0 1 0 com10 19 1 0 0 1 1 not fixed 0a 0 1 0 1 0 com11 1a 0 1 0 1 1 not fixed 0b 1 1 0 1 0 com12 1b 1 1 0 1 1 not fixed 0c 0 0 1 1 0 com13 1c 0 0 1 1 1 not fixed 0d 1 0 1 1 0 com14 1d 1 0 1 1 1 not fixed 0e 0 1 1 1 0 com15 1e 0 1 1 1 1 not fixed 0f 1 1 1 1 0 com16 1f 1 1 1 1 1 not fixed c0 c1 c2 c3 c4 c5 c6 c7 b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (26th) lsb msb c0 c1 c2 c3 c4 c5 c6 c7 b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (33rd) lsb msb : specifies the character codes of dummy cgrom and cgram (not written into dcram address) : specifies the character codes of dummy cgrom and cgram (not written into dcram address) b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (34th) lsb msb : specifies the character codes of cgrom and cgram (dcram address 00h is rewritten) c0 c1 c2 c3 c4 c5 c6 c7 (operated 8 times)
fedl9207-02 oki semiconductor ML9207-XX 18/35 2. cgram data write (specifies the addresses of cgram and writes character pattern data.) cgram (character generator ram) has a 4-bit address to store 5 7 dot matrix character patterns. a character pattern stored in cgram can be displayed by specifying the character code (address) by dcram. the address of cgram is assigned to 00h to 0fh. (all the other addresses are the cgrom addresses.) (the cgram can store 16 types of character patterns.) [command format] to specify character pattern data continuously to the next address, specify only character pattern data as follows. the addresses of cgram are automatically incremented. specification of an address is therefore unnecessary. the 2nd to 6th byte (character pattern data) are regarded as one data item, so 250 ns is sufficient for t doff time between bytes. c0 c5 c10 c15 c20 c25 c30 * b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (2nd) lsb msb : specifies 1st column data (written into cgram address 00h) c1 c6 c11 c16 c21 c26 c31 * b0 b1 b2 b3 b4 b5 b6 b7 3rd byte (3rd) lsb msb : specifies 2nd column data (written into cgram address 00h) x0 x1 x2 x3 * 0 1 0 b0 b1 b2 b3 b4 b5 b6 b7 1st byte (1st) lsb msb : selects cgram data write mode and specifies cgram address. (ex: specifies cgram address 00h.) c2 c7 c12 c17 c22 c27 c32 * b0 b1 b2 b3 b4 b5 b6 b7 4th byte (4th) lsb msb : specifies 3rd column data (written into cgram address 00h) c3 c8 c13 c18 c23 c28 c33 * b0 b1 b2 b3 b4 b5 b6 b7 5th byte (5th) lsb msb : specifies 4th column data (written into cgram address 00h) c4 c9 c14 c19 c24 c29 c34 * b0 b1 b2 b3 b4 b5 b6 b7 6th byte (6th) lsb msb : specifies 5th column data (written into cgram address 00h)
fedl9207-02 oki semiconductor ML9207-XX 19/35 x0 (lsb) to x3 (msb) : cgram addresses (4 bits: 16 characters) c0 (lsb) to c34 (msb) : character pattern data (35 bits: 35 outputs per digit) * : don't care c0 c5 c10 c15 c20 c25 c30 * b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (7th) lsb msb : specifies 1st column data (written into cgram address 01h) c4 c9 c14 c19 c24 c29 c34 * b0 b1 b2 b3 b4 b5 b6 b7 6th byte (11th) lsb msb : specifies 5th column data (written into cgram address 01h) c0 c5 c10 c15 c20 c25 c30 * b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (12th) lsb msb : specifies 1st column data (written into cgram address 02h) c4 c9 c14 c19 c24 c29 c34 * b0 b1 b2 b3 b4 b5 b6 b7 6th byte (16th) lsb msb : specifies 5th column data (written into cgram address 02h) c0 c5 c10 c15 c20 c25 c30 * b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (77th) lsb msb : specifies 1st column data (written into cgram address 0fh) c4 c9 c14 c19 c24 c29 c34 * b0 b1 b2 b3 b4 b5 b6 b7 6th byte (81st) lsb msb : specifies 5th column data (written into cgram address 0fh) c0 c5 c10 c15 c20 c25 c30 * b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (82nd) lsb msb : specifies 1st column data (cgram address 00h is written) c4 c9 c14 c19 c24 c29 c34 * b0 b1 b2 b3 b4 b5 b6 b7 6th byte (86th) lsb msb : specifies 5th column data (cgram address 00h is written)
fedl9207-02 oki semiconductor ML9207-XX 20/35 [cgrom addresses and set cgram addresses] refer to romcode table hex x0 x1 x2 x3 cgrom address hex x0 x1 x2 x3 cgrom address 00 0 0 0 0 ram00(00000000b) 08 0 0 0 1 ram08(00001000b) 01 1 0 0 0 ram01(00000001b) 09 1 0 0 1 ram09(00001001b) 02 0 1 0 0 ram02(00000010b) 0a 0 1 0 1 ram0a(00001010b) 03 1 1 0 0 ram03(00000011b) 0b 1 1 0 1 ram0b(00001011b) 04 0 0 1 0 ram04(00000100b) 0c 0 0 1 1 ram0c(00001100b) 05 1 0 1 0 ram05(00000101b) 0d 1 0 1 1 ram0d(00001101b) 06 0 1 1 0 ram06(00000110b) 0e 0 1 1 1 ram0e(00001110b) 07 1 1 1 0 ram07(00000111b) 0f 1 1 1 1 ram0f(00001111b) positional relationship between the output area of cgrom and that of cgram note: cgrom (character generator rom) has an 8-bit address to generate 5 7 dot matrix character patterns. cgram can store 240 types of character patterns. general-purpose code -01 is available and custom codes are provided on customer's request. c0 c5 c10 c15 c20 c25 c30 c1 c6 c11 c16 c21 c26 c31 c2 c7 c12 c17 c22 c27 c32 c3 c8 c13 c18 c23 c28 c33 c4 c9 c14 c19 c24 c29 c34 area that corresponds to 2nd byte (1st column) area that corresponds to 3rd byte (2nd column) area that corresponds to 5th byte (4th column) area that corresponds to 6th byte (5th column) area that corresponds to 4th byte (3rd column)
fedl9207-02 oki semiconductor ML9207-XX 21/35 3. adram data write (specifies the addresses 00h to 1fh of adram and writes symbol data.) adram (additional data ram) has a 5-bit address to store symbol data. symbol data specified by adram is directly output without cgrom and cgram. (the adram can store 4 types of symbol patterns for each digit.) the terminal to which the contents of adram are output can be used as a cursor. [command format] to specify symbol data continuously to the next address, specify only symbol data as follows. the address of adram is automatically incremented. specification of addresses is therefore unnecessary. c0 c1 c2 c3 * * * * b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (2nd) lsb msb : sets symbol data (written into adram address 00h.) x0 x1 x2 x3 x4 1 1 0 b0 b1 b2 b3 b4 b5 b6 b7 1st byte (1st) lsb msb : selects adram data write mode and specifies adram address (ex: specifies adram address 00h.) c0 c1 c2 c3 * * * * b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (3rd) lsb msb : sets symbol data (written into adram address 01h) c0 c1 c2 c3 * * * * b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (4th) lsb msb : sets symbol data (written into adram address 02h) c0 c1 c2 c3 * * * * b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (25th) lsb msb : sets symbol data (written into adram address 17h)
fedl9207-02 oki semiconductor ML9207-XX 22/35 the symbol data setting up to 24 digits is completed. to set symbol data from adram address 00h continuously. specify a dummy symbol data between adram addresses 18h and 1fh. (to increment the adram address automatically and set it to 00h) x0 (lsb) to x4 (msb) : adram addresses (5 bits: 24 characters) c0 (lsb) to c3 (msb) : symbol data (4 bits: 4-symbol data per digit) * : don't care [com positions and adram addresses] hex x0 x1 x2 x3 x4 com position hex x0 x1 x2 x3 x4 com position 00 0 0 0 0 0 com1 10 0 0 0 0 1 com17 01 1 0 0 0 0 com2 11 1 0 0 0 1 com18 02 0 1 0 0 0 com3 12 0 1 0 0 1 com19 03 1 1 0 0 0 com4 13 1 1 0 0 1 com20 04 0 0 1 0 0 com5 14 0 0 1 0 1 com21 05 1 0 1 0 0 com6 15 1 0 1 0 1 com22 06 0 1 1 0 0 com7 16 0 1 1 0 1 com23 07 1 1 1 0 0 com8 17 1 1 1 0 1 com24 08 0 0 0 1 0 com9 18 0 0 0 1 1 not fixed 09 1 0 0 1 0 com10 19 1 0 0 1 1 not fixed 0a 0 1 0 1 0 com11 1a 0 1 0 1 1 not fixed 0b 1 1 0 1 0 com12 1b 1 1 0 1 1 not fixed 0c 0 0 1 1 0 com13 1c 0 0 1 1 1 not fixed 0d 1 0 1 1 0 com14 1d 1 0 1 1 1 not fixed 0e 0 1 1 1 0 com15 1e 0 1 1 1 1 not fixed 0f 1 1 1 1 0 com16 1f 1 1 1 1 1 not fixed c0 c1 c2 c3 * * * * b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (26th) lsb msb : sets dummy symbol data (not written into adram address) c0 c1 c2 c3 * * * * b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (33rd) lsb msb : sets dummy symbol data (not written into adram address) c0 c1 c2 c3 * * * * b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (34th) lsb msb : sets dummy symbol data (adram address 00h is rewritten)
fedl9207-02 oki semiconductor ML9207-XX 23/35 4. general output port set (specifies the general output port status.) the general output port is an output for 4-bit static operation. when the reset signal is input, the general output ports go ?low?. (see ?reset function?) it is used to control other i/o devices and turn on led. (static operation) when at the "high" level, this output becomes the v dd voltage, and when at the "low" level, it becomes the ground potential. therefore, the fluorescent display tube cannot be driven. [command format] p1 to p4 : general output ports * : don't care [set data and set state of general output port] pn display state of general output port 0 sets the output to low 1 sets the output to high (the state when reset signal is input.) p1 p2 p3 p4 * 0 0 1 b0 b1 b2 b3 b4 b5 b6 b7 1st byte lsb msb : selects a general output port and specifies the output status
fedl9207-02 oki semiconductor ML9207-XX 24/35 5. display duty set (writes a display duty value to the duty cycle register.) display duty adjusts brightness in 960 stages (0/1024 to 960/1024) using 10-bit data. when the reset signal is input, the duty cycle register value is "0". (see "reset function") always execute this instruction before turning the display on, then set a desired duty value. [command format] d0 (lsb) to d9 (msb) : display duty data (10 bits: 0/1024 to 960/1024 stages) * : don't care [relation between setup data and controlled com duty] hex d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 com duty 000 0 0 0 0 0 0 0 0 0 0 0/1024 001 1 0 0 0 0 0 0 0 0 0 1/1024 002 0 1 0 0 0 0 0 0 0 0 2/1024 3be 0 1 1 1 1 1 0 1 1 1 958/1024 3bf 1 1 1 1 1 1 0 1 1 1 959/1024 3c0 0 0 0 0 0 0 1 1 1 1 960/1024 3c1 1 0 0 0 0 0 1 1 1 1 960/1024 3fe 0 1 1 1 1 1 1 1 1 1 960/1024 3ff 1 1 1 1 1 1 1 1 1 1 960/1024 (the state when reset signal is input.) d0 d1 * * * 1 0 1 b0 b1 b2 b3 b4 b5 b6 b7 1st byte (1st) lsb msb : selects display duty set and sets duty value (low-order 2 bits). d2 d3 d4 b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (2nd) lsb msb : sets duty value (high-order 8 bits). d5 d6 d7 d8 d9
fedl9207-02 oki semiconductor ML9207-XX 25/35 6. number of digits set (writes the number of display digits to the display digit register.) the number of digits set can display 9 to 24 digits using 4-bit data. when the reset signal is input, the number of digit register value is "0". (see ?reset function?) always execute this instruction to change the number of digits before turning the display on. [command format] k0 (lsb) to k3 (msb) : number of digit data (4 bits: 16 digits) * : don't care [relation between setup data and controlled com] hex k0 k1 k2 k3 number of digits of com hex k0k1k2k3 number of digits of com 0 0 0 0 0 com1 to 24 8 0 0 0 1 com1 to 16 1 1 0 0 0 com1 to 9 9 1 0 0 1 com1 to 17 2 0 1 0 0 com1 to 10 a 0 1 0 1 com1 to 18 3 1 1 0 0 com1 to 11 b 1 1 0 1 com1 to 19 4 0 0 1 0 com1 to 12 c 0 0 1 1 com1 to 20 5 1 0 1 0 com1 to 13 d 1 0 1 1 com1 to 21 6 0 1 1 0 com1 to 14 e 0 1 1 1 com1 to 22 7 1 1 1 0 com1 to 15 f 1 1 1 1 com1 to 23 * the state when reset signal is input. k0 k1 k2 k3 * 0 1 1 b0 b1 b2 b3 b4 b5 b6 b7 1st byte lsb msb : selects the number of digit set mode and specifies the number of digit value
fedl9207-02 oki semiconductor ML9207-XX 26/35 7. all display lights on/off set (turns all display lights on or off.) when the reset signal is input, all segment, common and ad outputs go ?low?. (see ?reset function?) all display lights on is used primarily for display testing. all display lights off is primarily used for display blink and to prevent malfunction when power is turned on. this command cannot control the general output port. [command format] [set data and display state of seg and ad] l h display state of seg and ad 0 0 normal display 1 0 sets all outputs to low 0 1 sets all outputs to high 1 1 sets all outputs to high (the state when reset signal is input.) l h * * * 1 1 1 b0 b1 b2 b3 b4 b5 b6 b7 1st byte lsb msb : selects all display lights on or off mode and specifies display operation l and h: display operation data * : don't care
fedl9207-02 oki semiconductor ML9207-XX 27/35 setting flowchart (power applying included) apply v fl all display lights off number of digits setting display duty setting cgram data write mode (with address setting) cgram character code cgram is character code another ram to be set? general output port setting releases all display lights off mode adram data write mode (with address setting) adram character code adram is character code dcram data write mode (with address setting) dcram character code dcram is character code select a ram to be used status of all outputs by reset signal input display operation mode no no no yes yes yes yes end apply v dd and v disp no address is automatically incremented address is automatically incremented address is automatically incremented write ended? write ended? write ended?
fedl9207-02 oki semiconductor ML9207-XX 28/35 power-off flowchart display operation mode turn off v dd and v disp turn off v fl
fedl9207-02 oki semiconductor ML9207-XX 29/35 application circuit notes: *1. the application circuit indicates a circuit by which fluorescent display tube filaments are ac driven using a heater transformer. contact fluorescent display tube manufacturers for the methods and circuits of driving fluorescent display tube filaments. *2. keep the wires between the osc0 pin and the crystal or ceramic resonator as short as possible to avoid generating noise. *3 for oscillation capacitor values, refer to data of the crystal or ceramic resonator used. ml9207 -xx micro- controller 24 35 4 r ese t v dd , v disp1-2 com1-24 seg1-35 ad1-4 v dd gnd gnd v fl1-2 osc0 osc1 da c p c s output port p1-4 r 3 c 3 c 4 v dd v fl zd 4 5 7-dot matrix fluorescent display tube grid (digit) anode (segment) anode (segment) heater transformer r 4 led v dd npn tr gnd gnd gnd crystal or ceramic resonator *1 *1 *1 *2 *3 gnd v dd
fedl9207-02 oki semiconductor ML9207-XX 30/35 reference data graphs illustrating the v fl versus driver output current capability relationship are shown below. care must be taken not to use the total power in excess of allowable power dissipation. ? 2.0 ? 1.5 ? 1.0 ? 0.5 0 0 ? 15 ? 30 ? 45 ? 60 ? 75 (ma) [v n(v)] disp ? [driver output current versus output drop volta g e] v = 60v, comn fl ? [output current (ma)] ? 2.0 ? 1.5 ? 1.0 ? 0.5 0 0 ? 4 ? 8 ? 12 ? 16 ? 20 (ma) [v n(v)] disp ? [driver output current versus output drop voltage] v = 60v, adn fl ? [output current (ma)] (v) (v) ta = 4 0 c ? ta = 2 5 c ta = 8 5 c ta = 4 0 c ? ta = 2 5 c ta = 8 5 c ? [ ?2.0 ? 1.5 ? 1.0 ? 0.5 0 0 ? 2 ? 4 ? 6 ? 8 ? 10 (ma) [v n(v)] disp ? [driver output current versus output drop voltage] v = 60v, segn fl ? [output current (ma)] (v) ta = 4 0 c ? ta = 2 5 c ta = 8 5 c ? 2.0 ? 1.5 ? 1.0 ? 0.5 0 0 ? 15 ? 30 ? 45 ? 60 ? 75 ( ma ) [v n(v)] disp ? [driver output current versus output drop volta g e] v = 20v, comn fl ? [output current (ma)] ? 2.0 ? 1.5 ? 1.0 ? 0.5 0 0 ? 4 ? 8 ? 12 ? 16 ? 20 (ma) [v n(v)] disp ? [driver output current versus output drop volta g e] v = 20v, adn fl ? [output current (ma)] (v) (v) ta = 4 0 c ? ta = 2 5 c ta = 8 5 c ? 2.0 ? 1.5 ? 1.0 ? 0.5 0 0 ? 2 ? 4 ? 6 ? 8 ? 10 (ma) [v n(v)] disp ? [driver output current versus output drop volta g e] v = 20v, segn fl ? [output current (ma)] (v) ta = 4 0 c ? ta = 2 5 c ta = 8 5 c ta = 4 0 c ? ta = 2 5 c ta = 8 5 c
fedl9207-02 oki semiconductor ML9207-XX 31/35 ml9207-01 rom code 00000000b (00h) to 00000111b (0fh) are the cgram addresses. msb 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 111 1 lsb 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 ram0 ram1 ram2 ram3 ram4 ram5 ram6 ram7 ram8 ram9 rama ramb ramc ramd rame ramf
fedl9207-02 oki semiconductor ML9207-XX 32/35 package dimensions notes for mounting the surface mount type package the surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact oki?s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). qfp80-p-1414-0.65-k mirror finish package material epoxy resin lead frame material 42 alloy pin treatment solder plating ( 5m) package weight (g) 0.85 typ. 5 rev. no./last revised 3/nov. 28, 1996 (unit: mm)
fedl9207-02 oki semiconductor ML9207-XX 33/35 notes for mounting the surface mount type package the surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact oki?s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). qfp80-p-1420-0.80-bk mirror finish package material epoxy resin lead frame material 42 alloy pin treatment solder plating ( 5m) package weight (g) 1.27 typ. 5 rev. no./last revised 4/nov. 28, 1996 (unit: mm)
fedl9207-02 oki semiconductor ML9207-XX 34/35 revision history page document no. date previous edition current edition description fedl9207-01 july 2000 ? ? final edition 1 1 1 title 15 7dotcharacter 16-digitdisplay controller/driver with character ram 15 7dotcharacter 24-digitdisplay controller/driver with character ram 31 31 rom code lsb 0001 msb 0111 fedl9207-02 may 17, 2005 - 34 added revision history
fedl9207-02 oki semiconductor ML9207-XX 35/35 notice 1. the information contained herein can change without notice owing to product and/or technical improvements. before using the product, please make sure that the information being referred to is up-to-date. 2. the outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. when planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. when designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. neither indemnity against nor license of a third party?s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. no responsibility is assumed by us for any infringement of a third party?s right which may result from the use thereof. 6. the products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). these products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. certain products in this document may need government approval before they can be exported to particular countries. the purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and n ecessary steps at their own expense for these. 8. no part of the contents contained herein may be reprinted or reproduced without our prior permission. copyright 2005 oki electric industry co., ltd.

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